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Makefile: set macro once (Solaris make, GNU make) - UNIX Programming

Hello, I have a question on a problem that is disturbing me for some time now. I want to set a variable in a Makefile by calling a shell command. This usually is done like this: SRC = `pwd` But in this case, `pwd` will be evaluated for each usage of the macro SRC. I only want the shell command to be evaluated *once*. With GNU "make" I can use the following syntax: SRC := $(shell pwd | sed 's:\(.*/src\)/.*:

:') In a directory "/home/heiner/src/misc" this will set SRC to "/home/heiner/src". Solaris "make" has the following syntax for the same purpose: ...

  1. #1

    Default Makefile: set macro once (Solaris make, GNU make)

    Hello,

    I have a question on a problem that is disturbing me for some
    time now.

    I want to set a variable in a Makefile by calling a shell
    command. This usually is done like this:

    SRC = `pwd`

    But in this case, `pwd` will be evaluated for each usage
    of the macro SRC. I only want the shell command to be evaluated
    *once*.

    With GNU "make" I can use the following syntax:

    SRC := $(shell pwd | sed 's:\(.*/src\)/.*:\1:')

    In a directory "/home/heiner/src/misc" this will set
    SRC to "/home/heiner/src".

    Solaris "make" has the following syntax for the same purpose:

    SRC:sh = pwd | sed 's:\(.*/src\)/.*:\1:'

    Does anybody know of a way to write a makefile in a way
    both "make"s will accept it? Is there some common syntax
    both will accept? Or an if-then-else construct I could use?

    Heiner
    --
    ___ _
    / __| |_ _____ _____ _ _ Heiner STEVEN <heiner.stevennexgo.de>
    \__ \ _/ -_) V / -_) ' \ Shell Script Programmers: visit
    |___/\__\___|\_/\___|_||_| [url]http://www.shelldorado.com/[/url]

    Heiner Steven Guest

  2. #2

    Default Re: Makefile: set macro once (Solaris make, GNU make)

    %% Heiner Steven <heiner.stevennexgo.de> writes:

    hs> I want to set a variable in a Makefile by calling a shell
    hs> command. This usually is done like this:

    hs> SRC = `pwd`

    hs> But in this case, `pwd` will be evaluated for each usage
    hs> of the macro SRC. I only want the shell command to be evaluated
    hs> *once*.

    hs> Does anybody know of a way to write a makefile in a way both
    hs> "make"s will accept it? Is there some common syntax both will
    hs> accept? Or an if-then-else construct I could use?

    If your question is what you _implied_, which is there any way to get
    the `pwd` evaluated only once in a way that's portable between different
    variants of make, then the answer to all your questions above is "no".


    Personally I recommend that you write your makefiles in GNU make. That
    way you can use powerful features and still know your build environment
    is portable: GNU make is portable to every UNIX-like system, plus VMS,
    Windows, DOS, and Amiga. And a native OS/2 port will be in the next
    version.

    If you can't impose the requirement that users of your build system
    compile GNU make first, and you must use the native system make, then
    you will have to forego all special capabilities of all of them and
    write to the lowest common denominator, which is basically POSIX
    make... which is pretty low :).

    --
    -------------------------------------------------------------------------------
    Paul D. Smith <psmithgnu.org> Find some GNU make tips at:
    [url]http://www.gnu.org[/url] [url]http://make.paulandlesley.org[/url]
    "Please remain calm...I may be mad, but I am a professional." --Mad Scientist
    Paul D. Smith Guest

  3. #3

    Default Re: Makefile: set macro once (Solaris make, GNU make)

    Hi All!
    I just ran into the same issue - using a shell command in a makefile works differently on Linux and SunOS machines. I eventually found a solution :-)
    I took advantage of the fact that 1) shell commands with a back-tick (`pwd`) DO get evaluated in a targets body/command section and, 2) variables specified on the command line override variables specified in the makefile itself.

    PWD = `pwd`

    ### this target calls make again specifying variables on the command line :-)
    all:
    -make PWD=$(PWD) real_target

    ### this target does the real work
    real_target: $(PWD)/test.c
    touch $(PWD/test.o



    Making "real_target" explicitly ( make real_target ) gives an error:
    make real_target
    make: Fatal error: Don't know how to make target ``pwd`/test.c'

    Just calling "make" works:
    make
    touch /home/oper/test.o
    Unregistered Guest

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